Geek Cool:

Supercomputing for the masses?

Even discounting the marketing hype and recognizing the multithreading being implemented by both AMD and Intel in their latest, highest performing microprocessors, a new architecture in development by IBM, Toshiba, and Sony may be the next wave in adding "thinking power" to everything. From EE Times:

The eagerly anticipated Cell processor from IBM, Toshiba and Sony leverages a multicore 64-bit Power architecture with an embedded streaming processor, high-speed I/O, SRAM and dynamic multiplier in an effort, the partners hope, to revolutionize distributed computing architectures.

Although the technical aspects of the design, which has been in the works for nearly four years, are tightly held, details are emerging in excerpts from papers to be released today for the 2005 International Solid-State Circuits Conference, as well as in patent filings.

The highly integrated Cell device has been billed as a beefy engine for Sony's Playstation 3, due to be demonstrated in May. But the architecture also addresses many other applications, including set-top boxes and mobile communications. Workstations fitted with the Cell architecture — a $2 billion endeavor — are already in the hands of game developers.

Five ISSCC papers from members of the 400-strong Cell processor team (see related story, "Best Development Teams," page 64) open peepholes onto a highly modular and hierarchical first-generation device implemented in 90-nanometer silicon-on-insulator (SOI) technology.

At root, the Cell architecture rests on two concepts: the "apulet," a bundle comprising a data object and the code necessary to perform an action upon it; and the "processing element," a hierarchical bundle of control and streaming processor resources that can execute any apulet at any time.

The apulets appear to be completely portable among the processing elements in a system, so that tasks can be doled out dynamically by assigning a waiting apulet to an available processing element. Scalability can be achieved by adding processing elements.

These ideas are not easily achieved. According to data from Paul Zimmons, a PhD graduate in computer science from the University of North Carolina at Chapel Hill, they require a highly intelligent way of dividing memory into protected regions called "bricks," careful attention to memory bandwidth and local storage, and massive bandwidth between processing elements — even those lying on separate chips.

At the top level, the architecture appears to be a pool of "cells," or clusters of perhaps four identical processing elements. All of the cells in a system — or for that matter, a network of systems — are apparently peers. According to one of the ISSCC papers on the Cell design, a single chip implements a single processing element. The initial chips are being built in 90nm SOI technology, with 65nm devices reportedly sampling.

I'm not sure I see how this is significantly different from the standard parallel processing that has been the rage in supercomputing in the past few years, other than in this case the data to be processed and the code to process it appear to be grouped together into packets. Regardless, the parallel aspect of this architecture should allow even faster processing for higher resolution graphics and other processing intensive applications such as game-physics (Sony apparently plans this technology for use in their next generation PlayStation), control systems for car engines, active feedback applications (for example, using microphones to "hear" music and then compensate for inadequate speakers and room configuration to deliver perfect surround sound), more detailed medical imaging with instant analysis and comparison with historical data, and many other applications that do not immediately spring to my tired mind.

Incidentally, the research I do is directed towards the 45nm and beyond technology (for a company that is none of the those listed here), which is the follow-up to the 65nm technology mentioned above.